The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
One such creative packaging technique is the fabrication of interconnect structures, e.g., vias and metal lines. A complementary metal oxide semiconductor (CMOS) device may include a variety of semiconductor structures such as transistors, capacitors, resistors and/or the like. One or more conductive layers comprising metal lines are formed over the semiconductor structures and separated by adjacent dielectric layers. Vias are formed in the dielectric layers to provide an electrical connection between adjacent metal lines. In sum, metal lines and vias interconnect the semiconductor structures and provide a conductive channel between the semiconductor structures and the external contacts of the CMOS device.
A metal line and its adjacent via may be formed by using a dual damascene process. According to the fabrication process of a dual damascene structure, a dual damascene opening comprising a via portion and a trench portion is formed within a dielectric layer. The dual damascene opening may be formed by photolithography techniques known in the art. Generally, photolithography involves depositing a photoresist material and then irradiating (exposing) and developing in accordance with a specified pattern to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material from subsequent processing steps, such as etching. The etching process may be a wet or dry, anisotropic or isotropic, etch process, but preferably is an anisotropic dry etch process. After the etching process, the remaining photoresist material may be removed. It should also be noted that the damascene interconnect opening may be formed by one or more alternative process steps (e.g., a via first or a trench first damascene process).
After the dual damascene opening is formed, a barrier layer and a seed layer may be formed along the sidewalls and the bottom of the dual damascene opening. The barrier layer may be formed by suitable fabrication techniques such as various physical vapor deposition (PVD) techniques and the like. The seed layer may be formed by using suitable fabrication techniques such as PVD, electroless plating and the like.
Furthermore, an electroplating process may be applied to the dual damascene opening. As a result, the dual damascene opening is filled with a conductive material. The conductive material may comprise copper, although other suitable materials such as aluminum, alloys, tungsten, silver, doped polysilicon, combinations thereof, and/or the like, may alternatively be utilized.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.